As technological advances plunge deeper into submicron geometries, shallow trench isolation (STI) is replacing local oxidation of silicon (LOCOS) processes for the formation of isolation structures. STI processes advantageously allow for planarization of the entire substrate and isolation structure, thereby providing better control of a critical dimension (CD), e.g., when defining the gate stack of a transistor.
Conventional STI processing includes forming a pad oxide layer on a substrate, forming a pad nitride layer over the pad oxide layer, and forming a trench through the pad oxide and nitride layers in the substrate, as by reactive ion etching (RIE). A liner oxide is then thermally grown to anneal out any damage to and to passivate the substrate. The trench is then filled with an insulating material, typically an oxide, followed by chemical-mechanical polishing (CMP) such that the upper surface of the filled trench is substantially coplanar with the upper surface of the pad nitride layer. The pad nitride and oxide layers are then stripped resulting in the STI structure. Subsequent conventional processing includes forming transistors spaced apart by the STI.
In implementing STI, sharp corners are typically formed where the trench sidewall intersects the top surface of the substrate, adversely impacting device performance, yield, and liability. Typically, a parasitic transistor having a relatively low threshold voltage is formed at the trench corner. Such parasitic transistors result in a high leakage issues and degrade Ion-Ioff performance, in addition to increasing linear threshold voltage (Vtlin) mismatch. Conventional approaches to the parasitic transistor issue involve rounding the transistor corner in attempting to reduce the electric field, and additional field implants to increase the threshold voltage of the parasitic transistor. Such approaches have not met with complete success, become increasingly more difficult as geometries plunge, and adversely impact STI efficacy.
A need therefore exists for methodology enabling the fabrication of semiconductor devices having STI structures with reduced leakage current, reduced degradation of Ion-Ioff performance, and reduced Vtlin mismatch. A particular need exists for methodology enabling the fabrication of semiconductor devices with CDs in the deep submicron range, wherein parasitic transistors formed at trench corners exhibit an increased threshold voltage and reduced mobility.